The present invention relates to the field of semiconductor integrated circuits; more specifically, it relates to a structure for reducing shallow trench isolation (STI) bound inter-well leakage in complementary metal oxide semiconductor (CMOS) technology and the method of fabricating said structure.
Bulk CMOS technologies that utilize STI can be susceptible to leakage currents between the N-well or the P-well and adjacent diffusions or the substrate that the STI attempts to isolate. STI is formed by etching a trench from the surface of a substrate a predetermined depth into the substrate and then filling the trench with an insulator. Inter-well leakage is a key design issue that affects the degree to which performance-influencing parameters such as junction capacitance can be optimized. Inter-well leakage can cause latch-up, high standby current and high power dissipation. Inter-well leakage becomes increasingly important as the design ground-rules for STI shrink in response to increased device density.
Turning to FIG. 1, FIG. 1 is a partial cross-section view through a typical pair of CMOS devices. Fabricated on a substrate 100 are a PFET 105 and an NFET 110. PFET 105 is bounded by a first STI 115 and a second STI 120. NFET 110 is bounded by second STI 120 and a third STI 125. PFET 105 is fabricated in an N-well 130 and comprises source/drains 135A, 135B, and a gate 140. NFET 110 is fabricated in a P-well 145 and comprises source/drains 150A, 150B, and a gate 155. An isolation junction 160 is formed between N-well 130 and P-well 145 and extends up to a bottom surface 165 of second STI 120. Isolation junction 160 and second STI 120 provide for isolation of PFET 105 and NFET 110.
FIGS. 2A and 2B are partial cross section views illustrating one method of forming an N-well and a P-well in CMOS technology. In FIG. 1, second STI 120 is formed in substrate 100. Second STI 120 has in addition to bottom surface 165, a first sidewall 170 and a second sidewall 175. Second STI 120 is bisected by a reference plane 180, which is equidistant from first and second sidewalls 170 and 175 and perpendicular to a top surface 182 of substrate 100. N-well 130 is formed by implantation of N dopant atoms using a first resist mask 185 as an implantation mask. First resist mask 185 has a sidewall 187 formed on top of second STI 120 and between reference plane 180 and first sidewall 170 of the second STI. After implant, a sidewall 188 of N-well 130 is located under second STI 120 and between reference plane 180 and first sidewall 170 of the second STI.
In FIG. 2B, P-well 145 is formed by implantation of P dopant atoms using a second resist mask 190 as an implantation mask. Second resist mask 190 has a sidewall 197 formed on top of second STI 120 and between reference plane 180 and second sidewall 175 of the second STI. After implant, a sidewall 198 of P-well 145 is located under STI 120 and between reference plane 180 and second sidewall 175 of the second STI. Sidewall 188 of N-well 130 is separated from sidewall 198 of P-well 145 by distance xe2x80x9cDxe2x80x9d. After subsequent process steps, especially heat cycles, sidewall 188 of N-well 130 and sidewall 198 of P-well 145 merge due to dopant diffusion to form isolation junction 160 as illustrated in FIG. 1 and described above. Generally, the N-well and P-well implants are not necessarily performed directly on surface 182 of substrate 100, but through an intervening layer, which may comprise silicon oxide, silicon nitride, or a combination thereof, formed on the surface of the substrate, which layer has not been included in FIGS. 2A and 2B.
FIG. 3 is a partial cross-section view through a typical pair of CMOS devices illustrating a leakage path between the P-well device and the N-well. Non-perfect or misalignment of first and/or second resist masks 185 and 190 will cause isolation junction 160 to shift further toward NFET 110 and result in increased inter-well leakage. The leakage path is from grounded source/drain 150A of NFET 110 to N-well 130 held at VNW. In one example, VNW is about 0 to 2.5 v. As the width of second STI 120 decreases, the percent the total width of the second STI used by alignment tolerances increases, so even acceptable alignment can result in unacceptable inter-well leakage. Decrease in the depth of second STI 120 also increases inter-well leakage.
Accordingly, a method to control inter-well leakage as STI width and depth ground-rules decrease is required.
A first aspect of the present invention is a method of forming a semiconductor device with improved leakage control, comprising: providing a semiconductor substrate having a top surface; forming a trench in the substrate, the trench having a bottom, a first sidewall and an opposite second sidewall; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to the second sidewall; filling the trench with an insulator; and forming an N-well in the substrate adjacent to and in contact with the first sidewall, the N-well extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench.
A second aspect of the present invention is a method of forming a semiconductor device with improved leakage control, comprising: providing a P doped semiconductor substrate having a top surface; forming a trench in the substrate, the trench having a bottom, a first sidewall and an opposite second sidewall; forming a conformal modulating layer on the top surface of the substrate and on the bottom and first and second sidewalls of the trench; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to the second sidewall; filling the trench with an insulator; and forming an N-well in the substrate adjacent to and in contact with the first sidewall, the N-well extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench.
A third aspect of the present invention is a semiconductor device with improved leakage control, comprising: a P doped semiconductor substrate having a top surface; a STI in the substrate, the STI having a bottom, a first sidewall and an opposite second sidewall; a leakage stop implant in the substrate under the bottom of the STI and under and aligned to the second sidewall; and an N-well in the substrate adjacent to and in contact with the first sidewall, the N-well extending under the STI and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the STI.
A fourth aspect of the present invention is a method of forming a semiconductor device with improved leakage control, comprising: providing a semiconductor substrate having a top surface; forming a trench in the substrate, the trench having a bottom, a first sidewall and an opposite second sidewall; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to the second sidewall; filling the trench with an insulator; and forming a P-well in the substrate adjacent to and in contact with the first sidewall, the P-well extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench.
A fifth aspect of the present invention is a method of forming a semiconductor device with improved leakage control, comprising: providing an N doped semiconductor substrate having a top surface; forming a trench in the substrate, the trench having a bottom, a first sidewall and an opposite second sidewall; forming a conformal modulating layer on the top surface of the substrate and on the bottom and first and second sidewalls of the trench, the modulating layer having a outer surface; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to the outer surface of the modulating layer on the second sidewall; filling the trench with an insulator; and forming a P-well in the substrate adjacent to and in contact with the first sidewall, the P-well extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench.
A sixth aspect of the present invention is a semiconductor device with improved leakage control, comprising: an N doped semiconductor substrate having a top surface; a STI in the substrate, the STI having a bottom, a first sidewall and an opposite second sidewall; a leakage stop implant in the substrate under the bottom of the STI and under and aligned to the second sidewall; and a P-well in the substrate adjacent to and in contact with the first sidewall, the P-well extending under the STI and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the STI.